(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming buried contact or a contact to the emitter regions of a bipolar transistor in the fabrication of integrated circuits.
(2) Description of the Prior Art
A typical buried contact process flow is to form an opening to the silicon substrate over the planned source/drain regions of a field effect transistor or emitter regions of a bipolar transistor, then deposit a doped layer of polysilicon over and on the planned regions. The structure is heated and the source/drain regions or emitter regions are formed by outdiffusion from the doped polysilicon layer. The doped polysilicon layer is allowed to remain on the source/drain regions or emitter regions as their contacts. This is called the buried contact process.
In forming buried contact to source/drain or emitter regions, some native silicon oxide forms on the surface of the silicon substrate. This results in some residue islands of silicon oxide in the polysilicon crystal interface which increases the contact resistance or the emitter resistance/current rating. Workers in the art believe that it is desirable to remove this native silicon oxide.
Some workers in the field have addressed this issue of unwanted silicon oxide. U.S. Pat. No. 4,597,159 to Usami et al describes a process of forming a semiconductor device in which the atmosphere in which a polysilicon film is deposited does not contain sufficient oxygen for oxidation of the polysilicon to take place. U.S. Pat. No. 4,800,179 to Mukai describes a process for removing native oxide formed on an aluminum layer via laser pulses through a second aluminum layer. Akinci et al show that a contaminating silicon oxide layer can be removed by annealing at approximately 850.degree. C. for 2 to 10 minutes. ("NiSi.sub.2 On Si(111): 1. Effects of substrate cleaning procedure and reconstruction," by G. Akinci, T. R. Ohno, and Ellen D. Williams, Surface Science 193 (1988) p. 534-548, North-Holland, Amsterdam).
The process of the present invention utilizes a multiple layer structure. Multiple layers have been used in a number of U.S. Patents, although they are composed of different materials and/or they are used for different purposes that those of the present invention. For example, U.S. Pat. No. 4,829,024 to Klein et al describes a process of forming a metal barrier layer within a contact opening followed by the deposition and etchback of multiple polysilicon layers in order to limit grain size in the polysilicon layers. U.S. Pat. No. 4,354,309 to Gardiner et al describes a multiple polysilicon layer used in forming a gate which reduces grain growth and void formation in the polysilicon. U.S. Pat. No. 4,329,706 to Crowder et al details an improved interconnection for semiconductor integrated circuits using layers of polysilicon and metal silicide. U.S. Pat. No. 5,093,700 to Sakata describes a gate structure formed using multiple alternating layers of polysilicon and silicon oxide to reduce grain size and improve resistance of the transistor.
The problem of native oxide islands within the polysilicon and buried contact to source/drain or emitter region interface remains to be addressed by the present invention.